CV

R&D Intern

Synopsys Inc

PrimeTime, PrimeShield, Workload-dependent Aged STA, Aging(BTI/HCI) Mission Profile

• Assisted the development of a machine learning-accelerated workload-dependent aging-aware STA approach. The new approach counted in the DVFS usage by supporting the scalability of the BTI/HCI aging mission profiles, provided more accurate STA simulation on the actual path, and preventing overly pessimistic aging derates in the current PrimeTime tool. Meanwhile, a one-shot pipeline was developed with Python to overcome the productivity bottleneck from months to one day.

PhD

University of California, Riverside

Electrical Engineering

MS

University of California, Riverside

Computer Engineering

BS

Huazhong University of Science and Technology

Electrical Engineering

Machine Learning (ML)-Accelerated On-chip Power Grid EM-Aware Voltage Failure Fixing

Electronic Design Automation (EDA), Copper Interconnect Reliability, Electromigration(EM), EM/IR, On-chip Power Grid, Machine Learning, Generative AI Models, Optimization

• Utilized Physics Informed Neural Network (PINN) to develop a model for solving partial differential equation based Korhonen equations, enabling efficient Electromigration(EM) stress analysis.
• Applied generative AI models, including generative adversarial networks (GAN), variational autoencoder (VAE) and Vi-Transformer to quickly predict the power grid's EM-aware voltage.
• Modeled EM-aware on-chip power grid fixing scenario as an optimization problem, accelerate the optimization solving process by Machine Learning model acquired sensitivity data (PyTorch AutoGradient) to skip the circuit analysis-based sensitivity calculation.

Improving Device Aging Reliability (TDDB, BTI/HCI) with Approximate Computing (AC) Divider

EDA, Design Automation, Silicon Device Reliability (TDDB, BTI/HCI), Approximate Computing

• Proposed a SOTA approximate stochastic computing divider design that achieves the highest accuracy (close to the theoretical upper limit) and the lowest energy cost among all divider designs.
• Implemented the proposed divider design with Verilog. Functionality test by Synopsys VCS, Synthesis ASIC design with Synopsys Design Compiler.

Improving ML Hardware Accelerator Aging Reliability and Performance with AC Multiplier

EDA, Silicon Device Reliability, Machine Learning Hardware Accelerator, Neural Network Quantization, FPGA

• Proposed an approximate stochastic computing multiplier, which can compensate for the delay increase caused by BTI/HCI by reducing the demand computation cycles, and mitigating TDDB-induced errors by including error tolerance encoding.
• Embedded the proposed approximate computing multiplier in the neural network accelerator, which enables the neural network accelerator to trade-off among throughput, accuracy, and power during the inference stage by adjusting the bit-width.
• Started from neural network quantization by PyTorch, and implemented hardware design on Vivado FPGA with C++.

GridVAE: Fast Power Grid EM-Aware IR Drop Prediction and Fixing Accelerated by Variational AutoEncoder

IEEE/ACM 25th International Symposium on Quality Electronic Design (ISQED)

Fast and Scaled Counting-Based Stochastic Computing Divider Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and System (TCAD)

GridNetOpt: Fast Full-Chip EM-Aware Power Grid Optimization Accelerated by Deep Neural Networks

IEEE TCAD

COSAIM: Counter-based Stochastic-behaving Approximate Integer Multiplier for Deep Neural Networks}

ACM/IEEE 58th Design Automation Conference (DAC)

Approximate Divider Design Based on Counting-Based Stochastic Computing Division

ACM/IEEE 3rd Machine Learning for CAD (MLCAD)

Runtime Long-Term Reliability Management Using Stochastic Computing in Deep Neural Networks

IEEE/ACM 22nd ISQED

EMSpice: Physics-Based Electromigration Check Using Coupled Electronic and Stress Simulation}

IEEE