Yibo Liu

picture_yibo_lab.jpg

VLSI System and Computation Lab,

University of California, Riverside

CA, US

Ph.D. Student from VLSI System and Computation lab, University of California, Riverside. Specializing in machine learning acceleration techniques for VLSI reliability modeling and optimization. Experience in VLIS methodologies with machine learning applications, fault-tolerant computing, reliability-aware (EM, BTI, HCI, TBBD) design and management at both circuit and system levels. Experience in STA considering OCV and SSTA. Experience in Generative AI models (GAN, VAE, Vision Transformer) and machine learning accelerator design (power, performance, area trade-off).

selected publications

  1. Fast and Scaled Counting-Based Stochastic Computing Divider Design
    Yibo Liu, Shuyuan Yu, Maliha Tasnim , and 1 more author
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and System (TCAD), 2024
    HTML
  2. GridVAE: Fast Power Grid EM-Aware IR Drop Prediction and Fixing Accelerated by Variational AutoEncoder
    Yibo Liu, and Sheldon X.-D. Tan
    IEEE/ACM 25th International Symposium on Quality Electronic Design (ISQED), 2024
    HTML